This invention is related to integrated circuit devices having memory cell arrays and, in particular, to arrays capable of holding information without power and of being programmed multiple times.
An MTP (Multiple Times Programmable) device is a type of non-volatile memory device (NVM) that, as the name implies, can be programmed and erased numerous times. Once programmed, an MTP device can hold the programmed information even without power. Memories with MTP devices are found embedded in integrated circuits, such as microcontrollers, in many different types of computer systems, including smart phones, and independently as thumb drives which are carried on one's person and can be connected externally to a computer system (typically through a USB port).
It should be noted that often terms, such as MTP device and NVM device, are used interchangeably between the memory array, or the integrated circuit containing the array, and the memory cell, or the transistor-level element which stores programmed information. Hence care should be taken in determining what the term refers to. MTP device as used herein refers to a transistor-level element which stores programmed information unless the context clearly indicates otherwise.
At the transistor-level, an MTP device is a Field Effect Transistor (FET) device, also often referred to as a MOSFET (metal-oxide-semiconductor FET) in which the threshold voltage VT is determined by the charges in a charge storage region, such as a floating gate, or a plane or sidewall of charge trapping material in the gate region of transistor device. Nitride-based materials are examples of charge trapping materials and can form charge trapping structures, such as SONOS (Silicon-Oxide-Nitride-Oxide-Silicon layers), formed either as plane or a sidewall.
MTP memory cells face problems of scaling, i.e., problems resulting from the shrinkage in device feature size, particularly for semiconductor processes having critical dimensions of 40 nm (nanometer) or smaller. These problems include the requirements of thinner oxide layers, lower practical programming and erase voltages, smaller quantities of stored charge, and increasing variations in device parameters and performance, such as leakage and operating currents. Furthermore, Read operations should become faster with smaller features, but better access times are difficult to address in light of these problems of scaling. Furthermore, rather than a conventional NVM device in which the charge is stored in a floating gate, current MTP memory cells envision charge trapping in a sidewall of the device. This results in smaller differences in the threshold voltages between the Programmed and Erased states that must still be discriminated.
Hence what is needed is a MTP memory cell which can be easily scaled with future processes and which can solve or at least ameliorate the problems above.